1. Field of the Invention
The present relates to the manufacture and packaging of semiconductor devices. More particularly, the present invention relates to techniques for improving the reliability of semiconductor devices by implementing metallization features that resist plastic deformation during wiring bonding operations.
2. Description of the Related Art
As is well known, semiconductor chips are made by fabricating active devices in a semiconductor substrate and then fabricating various interconnect layers to define the desired integrated circuit device. To facilitate discussion, FIG. 1A illustrates a top view of a semiconductor chip 10 having a core region 12 and a plurality of input/output (I/O) conductive pads 14 defined along the periphery. The I/O conductive pads 14 are generally interconnected to underlying metallization features through the use of conductive vias, which provide the electrical contact to the circuits of the semiconductor chip 10. Once the semiconductor chip 10 is placed into a package, the I/O conductive pads 14 are coupled to leads of the package using a wire bonding process.
FIG. 1B illustrates a partial cross-sectional view of the semiconductor chip 10 during a conventional gold wire bonding process. This conventional wire bonding process is currently being used for a majority of semiconductor circuits due to its ability to form strong bonds to the top layers of I/O metallization pads and its efficient use in applications where the I/O pads are relatively small. Although this conventional gold wire bonding process is preferred over others, it also presents several reliability problems. As shown in FIG. 1B, a capillary 16 (of a wire bonding apparatus) is used to apply a gold wire bond 18 to a top surface of a metal I/O conductive pad 14. In order to ensure that the bond is secure, the capillary applies a substantial force "F" over the I/O conductive pad 14 while implementing a sufficiently elevated temperature to cause the gold wire bond to soften and expand at edges 18'.
An unfortunate problem is that the pressure and temperature that is needed to ensure a secure wire bond may damage underlying metal and inter-metal oxides (IMOs). For instance, FIG. 1B shows how the force F and temperature (and often ultrasonic energy) exerted by the wire bonding process may cause an IMO 20 to exert a corresponding force onto an underlying metallization layer 22. Because IMO 20 is substantially more dense (i.e., harder) and less susceptible to plastic deformation as is aluminum-type metallizations, the metallization layer 22 (of underlying patterned features) lying under the IMO 20 absorbs the most plastic deformation. In this example, the force F is shown to compress the metallization layer 22 the most in the area directly under the wire bond, thus bring the thickness of the metallization layer 22 from X to (X-.DELTA.X). In a location just outside of the wire bond, however, the metallization material is compressed to define a location in which the thickness of the metallization layer 22 grows from X to (X+.DELTA.X).
Beyond the plastic deformation of the metallization layer 22, which may lie over an IMO 24, the more rigid IMO 20 may also suffer in that it develops cracks 20a at the edges due to the large shear stress absorbed by the IMO 20. These cracks 20a become very problematic when features not intended to be electrically connected to the wire bonded pad are routed in an underlying metallization layer. This is because the cracks 20a essentially form conductive leakage links (i.e., electrical shorts) that force an unwanted electrical interconnection, thereby destroying the intended circuitry and operation of a chip.
FIG. 1C illustrates a top view of the semiconductor chip 10, in which a staggered two row bond pad arrangement is used to increase the density and pitch of bond pads 14 along the periphery of the chip. Accordingly, a first row of bond pads 14a and 14b are show connected by conductive vias down to underlying metallization lines 22a and 22b which may be connected to the core 12 of the chip. A second row of bond pads 14c, 14d and 14e are integrally connected to metallization lines 14c', 14d'and 14e', respectively. In this illustration, a gold wire bond 18/18' is made to I/O pad 14c, which is at least partially defined over the metallization line 22a. As discussed above, the wire bonding process is known to cause cracks 20a as shown in FIG. 1D, wherein the cracks 20a are formed in the IMO 20 that is defined between metallization layers. These cracks 20a will therefore define an unwanted electrically conductive connection between metallization line 14c' and 22a, which can result in a complete failure of the integrated circuit device.
Due to this known problem, design rules have been defined such that designers are discouraged or prohibited from patterning metallization features under I/O pads that will be receiving gold wire bonds. Accordingly, any metallization defined under bond pads may only be passive in that there are no active transistors and any underlying metal is either isolated or electrically connected to only the I/O pad receiving the gold wire bond. This therefore places a constraint on the allowed wiring density which necessarily forces the design of larger chips taking up more silicon, which consequently drives up the cost of the device.
One way to reduce failures due to cracks 20a is to reduce the downward bonding force and bonding temperature. However, this solution has the downside of producing weak and less reliable wire bonding. Accordingly, this solution does not help the reliability of the chip.
In view of the foregoing, there is a need for metallization features that are less resistant to plastic deformation and methods for making the deformation resistant metallization features. In conjunction with the need for deformation resistant features is the need for preventing crack formation in IMO layers in order to circumvent inadvertent shorts between layers.